Faculty of Computer Science and Information
Technology
Computer Organization and Architecture
Spring 2008
Instructors: Prof. Dr. Vladimir Radevski, Prof. Dr. Igor Trajkovski
Class Hours: Thursdays,
Classroom: Lab 1
Office Hours: Tuesdays,
E-mail address: Prof. Dr. Vladimir Radevski (radevski AT nyus DOT edu DOT mk),
Prof. Dr. Igor Trajkovski (trajkovski AT nyus DOT edu DOT mk)
Phone Number: +389 2 2034 632, +389 2 2034 636
Textbooks:
·
Computer Organization and Architecture: Designing for Performance; ; Prentice Hall; 6th edition
2003; ISBN-13: 978 - 0130351197
·
Computer
Architecture: A Quantitative Approach; John L. Hennessy (Author), David A.
Patterson; Morgan Kaufmann; 3rd edition 2002; ISBN-13: 978 - 1558605961
·
Additional material provided by
instructors
Course Description
This
is a course in computer organization with emphasis on the hierarchical
structure of computer systems. Covers topics such as: components of computer
systems and their configuration, design of basic digital circuits, the
microprogram level, the conventional machine level, the operating system level,
assembly language, addressing modes, interpreters/translators and computer
arithmetic.
vCourse Objectives
After
completing this course, students will be able to:
·
understand the important components of a computing system
·
learn how these components are interrelated
·
appreciate the problems and methods of designing computers
·
learn how certain operating system functions are supported by computer
hardware
·
see how various performance enhancements to computers are achieved (as
time permits), including pipelining, RISC architectures, and parallel
processing architectures
·
be able to make an informed comparison among competing architectures for
a given purpose
vGrading
The grade depends on the following:
Class participation 10%
Home work 20%
Midterm exam 30%
Final exam 40%
THERE WILL BE NO MAKE UP EXAMS
Weekly Plan
|
Week (1x3 classes) |
Theme |
Chapter |
Home Work |
|
1 [11.02.08] |
Introduction, Computer Evolution and Performance [VR] |
|
|
|
2 |
System Buses [VR] |
||
|
3 |
Cache Memory [IT] |
4 [PPT] |
|
|
4 |
Internal Memory [IT] |
5 [PPT] |
|
|
5 |
Input/Output & Operating System Support [VR] |
|
|
|
6 |
Computer Arithmetic [IT] |
9 [PPT] |
|
|
7 [24.03.08] |
Mid Term Exam |
Mid Term Exam |
|
|
8 |
Instruction Sets: characteristics, functions, addressing modes and formats [IT] |
|
|
|
9 |
SuperSim – simulator for ILP processors [IT] |
|
|
|
10 |
CPU Structure and Function [VR] |
12 |
|
|
11 |
Reduced Instruction Set Computers (RISK) [VR] |
13 |
|
|
12 [28.04.08] |
Easter Break |
|
|
|
13 |
Instruction Level Parallelism and Superscalar
Processors [VR] |
14 |
|
|
14 |
Parallel Processing [VR] |
18 |
|
|
15 |
Final Exam |
Final Exam |
|
vGrading Scale
|
A |
(4) |
10 |
93-100 |
|
B |
(3.2) |
9 |
85-92 |
|
C |
(2.4) |
8 |
77-84 |
|
D |
(1.6) |
7 |
69-76 |
|
E |
(0.8) |
6 |
61-68 |
|
F |
0 |
5 |
0-60 |